IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 124

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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Video and Image Processing Suite User Guide
Frame Rate Conversion
This configuration allows the input and output sides to swap asynchronously. When
the input finishes, it swaps with the spare frame if the spare frame contains data that
the output frame uses. Otherwise the function drops the frame which you have just
wrote and the function writes a fresh frame over the dropped frame.
When the output finishes, it also swaps with the spare frame and continues if the
spare frame contains fresh data from the input side. Otherwise it does not swap and
just repeats the last frame.
Triple-buffering allows simple frame rate conversion. For example, suppose you
connect the Deinterlacer’s input to a HDTV video stream in 1080i60 format and
connect its output i to a 1080p50 monitor. The input has 60 interlaced fields per
second, but the output tries to pull 50 progressive frames per second.
If you configure the Deinterlacer to output one frame for each input field, it produces
60 frames of output per second. If you enable triple-buffering, on average the function
drops one frame in six so that it produces 50 frames per second. If you chose one
frame output for every pair of fields input, the Deinterlacer produces 30 frames per
second output and triple-buffering leads to the function repeating two out of every
three frames on average.
When you select double or triple-buffering the Deinterlacer has two or more Avalon-
MM master ports. These must be connected to an external memory with enough space
for all of the frame buffers required. The amount of space varies depending on the
type of buffering and algorithm selected. An estimate of the required memory is
shown in the Deinterlacer parameter editor.
If the external memory in your system runs at a different clock rate to the Deinterlacer
MegaCore function, you can turn on an option to use a separate clock for the Avalon-
MM master interfaces and use the memory clock to drive these interfaces.
To prevent memory read and write bursts from being spread across two adjacent
memory rows, you can turn on an option to align the initial address of each read and
write burst to a multiple of the burst target used for the read and write masters (or the
maximum of the read and write burst targets if using different values). Turning on
this option may have a negative impact on memory usage but increases memory
efficiency.
When you select triple-buffering, the decision to drop and repeat frames is based on
the status of the spare buffer. Because the input and output sides are not tightly
synchronized, the behavior of the Deinterlacer is not completely deterministic and can
be affected by the burstiness of the data in the video system. This may cause
undesirable glitches or jerky motion in the video output.
By using a double-buffer and controlling the dropping/repeating behavior, the input
and output can be kept synchronized. For example, if the input has 60 interlaced
fields per second, but the output requires 50 progressive frames per second (fps),
setting the input frame rate to 30 fps and the output frame rate at 50 fps guarantees
that exactly one frame in six is dropped.
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Deinterlacer