IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 109

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Output
January 2011 Altera Corporation
Timing Constraints
Active Format Description Inserter
f
To constrain the Clocked Video Output MegaCore function correctly, add the
following file to your Quartus II project:
When you apply the SDC file, you may see some warning messages in a format as
follows:
■
■
These warnings are expected, because in certain configurations the Quartus II
software optimizes unused registers and they no longer remain in your design.
The AFD Inserter is an example of how to write a core to handle ancillary packets. It is
available in the following directory:
<install_dir>\ip\clocked_video_output\lib\afd_example
When the output of the AFD Inserter is connected to the input of the Clocked Video
Output MegaCore function, the AFD Inserter inserts an Avalon-ST Video ancillary
data packet into the stream after each control packet. The AFD Inserter sets the DID
and SDID of the ancillary packet to make it an AFD packet (DID = 0x41, SDID = 0x5).
The contents of the ancillary packet are controlled by the AFD Inserter register map.
Refer to the SMPTE 2016-1-2007 standard for a more detailed description of the AFD
codes.
Table 5–15
Table 5–15. AFD Inserter Register Map
Address
Warning: At least one of the filters had some problems and could not be matched.
Warning: * could not be matched with a keeper.
<install_dir>\ip\clocked_video_output\lib\alt_vip_cvo.sdc.
0
1
2
3
4
5
6
7
8
shows the AFD Inserter register map.
Bar data value 1
Bar data value 2
Bar data flags
AFD valid
Register
Control
AFD
AR
When bit 0 is 0, the core discards all packets.
When bit 0 is 1, the core passes through all non-
ancillary packets.
Reserved.
Reserved.
Bits 0-3 contain the active format description code.
Bit 0 contains the aspect ratio code.
Bits 0-3 contain the bar data flags to insert
Bits 0-15 contain the bar data value 1 to insert
Bits 0-15 contain the bar data value 2 to insert
When bit 0 is 0, an AFD packet is not present for each
image packet.
When bit 0 is 1, an AFD packet is present for each
image packet.
Video and Image Processing Suite User Guide
Description
5–29