IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 32

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–6
Video and Image Processing Suite User Guide
Complete the SOPC Builder System
1. Create a new Quartus II project using the New Project Wizard available from the
2. On the Tools menu, click SOPC Builder.
3. For a new system, specify the system name and language.
4. On the System Contents tab, double-click the name of your IP core to add it to
5. Specify the required parameters in the parameter editor. For detailed explanations
6. Click Finish to complete the IP core instance and add it to the system.
To complete the SOPC Builder system, follow these steps:
1. Add and parameterize any additional components. Some IP cores include a
2. Use the Connection panel on the System Contents tab to connect the components.
3. By default, clock names are not displayed. To display clock names in the Module
4. If you intend to simulate your SOPC builder system, on the System Generation
5. Click Generate to generate the system. SOPC Builder generates the system and
6. In the Quartus II software, click Add/Remove Files in Project and add the .qip file
7. Compile your design in the Quartus II software.
File menu.
your system. The relevant parameter editor appears.
of these parameters, refer to the “Parameter Settings” chapter in this document.
1
1
1
complete SOPC Builder system design example.
Name column and the clocks in the Clock column in the System Contents tab,
click Filters to display the Filters dialog box. In the Filter list, click All.
tab, turn on Simulation to generate simulation files for your system.
produces the <system name>.qip file that contains the assignments and
information required to process the IP core or system in the Quartus II Compiler.
to the project.
Some IP cores provide preset parameters for specific applications. If you
wish to use preset parameters, click the arrow to expand the Presets list,
select the desired preset, and then click Apply. To modify preset settings, in
a text editor edit the <installation directory>\ip\altera\uniphy\lib\<IP
core>.qprs file.
If your design includes external memory interface IP cores, you must turn
on Generate power of two bus widths on the PHY Settings tab when
parameterizing those cores.
The Finish button may be unavailable until all parameterization errors
listed in the messages window are corrected.
Chapter 2: Getting Started with Altera IP Cores
January 2011 Altera Corporation
SOPC Builder Design Flow