IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 173

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Gamma Corrector
Table 6–13. Frame Reader Signals (Part 2 of 2)
Gamma Corrector
Table 6–14. Gamma Corrector Signals (Part 1 of 2)
January 2011 Altera Corporation
slave_av_writedata
slave_av_irq
master_av_address
master_av_burstcount
master_av_read
master_av_readdata
master_av_readdatavalid
master_av_waitrequest
master_av_reset
master_av_clock
clock
reset
din_data
din_endofpacket
din_ready
Signal
Signal
Table 6–14
function.
shows the input and output signals for the Gamma Corrector MegaCore
Direction
In
In
In
In
Out
Direction
In
Out
Out
Out
Out
In
In
In
In
In
The main system clock. The MegaCore function operates on the rising
edge of the clock signal.
The MegaCore function is asynchronously reset when reset is asserted
high. The reset must be de-asserted synchronously with respect to the
rising edge of the clock signal.
din port Avalon-ST data bus. Pixel data is transferred into the MegaCore
function over this bus.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the
MegaCore function is ready to receive data.
slave port Avalon-MM writedata bus. These input
lines are used for write transfers.
slave port Avalon-MM interrupt signal. When
asserted the interrupt registers of the MegaCore function have
been updated and the master should read them to determine what
has occurred.
master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
master port Avalon-MM burstcount signal. Specifies
the number of transfers in each burst.
master port Avalon-MM read signal. Asserted to
indicate read requests from the master to the system interconnect
fabric.
master port Avalon-MM readdata bus. These input
lines carry data for read transfers.
master port Avalon-MM readdatavalid signal. This
signal is asserted by the system interconnect fabric when the
requested read data has arrived.
master port Avalon-MM waitrequest signal.
Asserted by the system interconnect fabric to cause the master
port to wait.
master port reset signal. The interface is reset
asynchronously when this signal is asserted high and must be de-
asserted synchronously with respect to the rising edge of the
clock signal.
master port The clock signal. The interface operates on
the rising edge of the clock signal.
Description
Description
Video and Image Processing Suite User Guide
6–17