EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 11
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Altera Corporation
Figure 3. LAB Structure
LEs drive local
MegaLAB, row,
and column
interconnects.
MegaLAB Interconnect
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
Row
Interconnect
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or
adjacent LABs, allowing the use of a fast local interconnect for high
performance.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Figure 3
APEX 20K Programmable Logic Device Family Data Sheet
shows the APEX 20K LAB.
Column
Interconnect
To/From
Adjacent LAB,
ESB, or IOEs
11
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