EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 71
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Part Number
Manufacturer
Quantity
Price
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Altera Corporation
Figure 39. ESB Synchronous Timing Waveforms
Rdaddress
Wraddress
ESB Synchronous Read
ESB Synchronous Write (ESB Output Registers Used)
Data-Out
Data-Out
Data-In
CLK
CLK
WE
WE
a0
t
ESBDATASU
a0
t
ESBWESU
din1
a1
Figure 40
dout0
a1
t
shows the timing model for bidirectional I/O pin timing.
ESBDATAH
t
ESBDATASU
dout1
APEX 20K Programmable Logic Device Family Data Sheet
din2
a2
t
t
ESBDATACO2
ESBDATAH
t
ESBSWC
din1
din3
t
a3
ESBWEH
t
ESBDATACO1
a2
t
ESBARC
din2
d1
din3
a2
a3
d2
din2
71
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