EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 54
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APEX 20K Programmable Logic Device Family Data Sheet
54
Notes to
(1)
(2)
(3)
(4)
SignalTap
Embedded
Logic Analyzer
f
IN
Table 18. APEX 20KE Clock Input & Output Parameters
Symbol
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
The maximum lock time is 40 µs or 2000 input clock cycles, whichever occurs first.
Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
The PLL VCO operating range is 200 MHz ð f
Tables 17
Input clock frequency
and 18:
Parameter
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
SSTL-2 Class
SSTL-2 Class
SSTL-3 Class
SSTL-3 Class
I/O Standard
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
LVDS
GTL+
VCO
II
II
I
I
ð 840 MHz for LVDS mode.
-1X Speed Grade
(Part 2 of 2)
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Max
290
281
272
303
291
291
300
300
420
Note (1)
-2X Speed Grade
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Altera Corporation
Max
257
250
243
261
253
253
260
260
350
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz