EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 56

• Manufacturer Part Number: EP20K100QC208-1
• Description: APEX 20K
• Manufacturer: Altera

Specifications of EP20K100QC208-1

• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 159
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

APEX 20K Programmable Logic Device Family Data Sheet
56
The APEX 20K device instruction register length is 10 bits. The APEX 20K
device USERCODE register length is 32 bits.
boundary-scan register length and device IDCODE information for
APEX 20K devices.
Note to
(1)
Table 20. APEX 20K Boundary-Scan Register Length
This device does not support JTAG boundary scan testing.
Table
EP20K1000E
EP20K1500E
20:
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K30E
EP20K60E
EP20K100
EP20K200
EP20K400
Device
Boundary-Scan Register Length
Tables 20
1,176
1,164
1,266
1,536
1,506
1,806
2,190
1
420
624
786
774
984
(1)
and
Altera Corporation
21
show the