EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 29

• Manufacturer Part Number: EP20K100QC208-1
• Description: APEX 20K
• Manufacturer: Altera

Specifications of EP20K100QC208-1

• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 159
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
Figure 16. APEX 20K Parallel Expanders
Embedded
System Block
Local Interconnect
32 Signals from
The ESB can implement various types of memory blocks, including
dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input
and output registers; the input registers synchronize writes, and the
output registers can pipeline designs to improve system performance. The
ESB offers a dual-port mode, which supports simultaneous reads and
writes at two different clock frequencies.
diagram.
Figure 17. ESB Block Diagram
Product-
Product-
Select
Select
Matrix
Matrix
Term
Term
APEX 20K Programmable Logic Device Family Data Sheet
wraddress[]
data[]
wren
inclock
inclocken
inaclr
Parallel
Expander Switch
Parallel
Expander Switch
Macrocell
Previous
From
Macrocell
Figure 17
To Next
rdaddress[]
outclocken
outclock
outaclr
rden
shows the ESB block
q[]
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic
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