EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 23
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
Figure 11
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
APEX 20KE devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow
interconnect without having to drive through the MegaLAB interconnect.
FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K300E
and larger devices, the FastRow interconnect drives the two MegaLABs in
the top left corner, the two MegaLABs in the top right corner, the two
MegaLABS in the bottom left corner, and the two MegaLABs in the
bottom right corner. On EP20K200E and smaller devices, FastRow
interconnect drives the two MegaLABs on the top and the two MegaLABs
on the bottom of the device. On all devices, the FastRow interconnect
drives all local interconnect in the appropriate MegaLABs except the local
interconnect on the side of the MegaLAB opposite the ESB. Pins using the
FastRow interconnect achieve a faster set-up time, as the signal does not
need to use a MegaLAB interconnect line to reach the destination LE.
Figure 12
™
shows the intersection of a row and column interconnect, and
shows the FastRow interconnect.
interconnect, which routes signals directly into the local
MegaLAB Interconnect
Row Interconnect
APEX 20K Programmable Logic Device Family Data Sheet
Interconnect
Local
LE
Column
Interconnect
23