EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 42

• Manufacturer Part Number: EP20K100QC208-1
• Description: APEX 20K
• Manufacturer: Altera

Specifications of EP20K100QC208-1

• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 159
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

APEX 20K Programmable Logic Device Family Data Sheet
42
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect.
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
Row Interconnect
LAB
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
Figure 27
shows how a row IOE connects to the
MegaLAB Interconnect
IOE
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
Altera Corporation