EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 18
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
APEX 20K Programmable Logic Device Family Data Sheet
Figure 8. APEX 20K LE Operating Modes
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
18
Normal Mode (1)
Arithmetic Mode
Counter Mode
LEs in normal mode support register packing.
There are two LAB-wide clock enables per LAB.
When using the carry-in in normal mode, the packed register feature is unavailable.
A register feedback multiplexer is available on LE1 of each LAB.
The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
data1 (5)
data2 (5)
data3 (data)
data1
data2
data3
data4
Figure
(4)
data1
data2
8:
Carry-In
Carry-In (3)
Carry-In
3-Input
3-Input
LUT
LUT
3-Input
3-Input
4-Input
LUT
LUT
LUT
Cascade-In
Cascade-In
Carry-Out
Carry-Out
Cascade-In
Cascade-Out
Cascade-Out
Cascade-Out
LAB-Wide
Synchronous
Load (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Clock Enable (2)
LAB-Wide
Clock Enable (2)
D
ENA
CLRN
PRN
D
ENA
CLRN
PRN
Q
ENA
D
Q
CLRN
PRN
Q
Altera Corporation
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out
LE-Out