EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 70
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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APEX 20K Programmable Logic Device Family Data Sheet
Figure 38. ESB Asynchronous Timing Waveforms
70
ESB Asynchronous Read
Rdaddress
ESB Asynchronous Write
Wraddress
Data-Out
Data-Out
Data-In
WE
RE
a0
a0
t
ESBWASU
d0
Figures 38
waveforms, respectively, for the ESB macroparameters in
din0
and
39
a1
t
ESBWCCOMB
show the asynchronous and synchronous timing
a1
t
t
ESBWP
ESBWDSU
din0
d1
t
din1
ESBDD
t
ESBWAH
t
ESBARC
din1
a2
t
ESBWDH
d2
Altera Corporation
Table
a2
dout2
a3
31.
d3
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