EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 45
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Altera Corporation
f
Figure 29. APEX 20KE I/O Banks
Notes to
(1)
(2)
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the V
supplies may be powered in any order.
For more information, please refer to the “Power Sequencing
Considerations” section in the Configuring APEX 20KE & APEX 20KC
Devices chapter of the Configuration Devices Handbook.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
LVDS/LVPECL
Block (2)
Output
I/O Bank 8
I/O Bank 7
For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for
Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE
Devices).
If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
V
CCIO
(1)
Figure
set to 3.3 V, 2.5 V, or 1.8 V.
29:
APEX 20K Programmable Logic Device Family Data Sheet
I/O Bank 6
I/O Bank 1
Regular I/O Blocks Support
■
■
■
■
■
■
■
■
■
■
■
■
LVTTL
LVCMOS
2.5 V
1.8 V
3.3 V PCI
LVPECL
HSTL Class I
GTL+
SSTL-2 Class I and II
SSTL-3 Class I and II
CTT
AGP
I/O Bank 2
I/O Bank 5
Individual
Power Bus
CCIO
and V
CCINT
I/O Bank 3
I/O Bank 4
(1)
LVDS/LVPECL
Block (2)
power
Input
45