EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 43

APEX 20K

EP20K100QC208-1

Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet

Specifications of EP20K100QC208-1

Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

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Part Number:
EP20K100QC208-1
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Figure 28. Column IOE Connection to the Interconnect
Altera Corporation
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
Row Interconnect
Figure 28
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow interconnect. Each IOE data
and OE signal is driven by local interconnect.
IOE
shows how a column IOE connects to the interconnect.
MegaLAB Interconnect
APEX 20K Programmable Logic Device Family Data Sheet
LAB
IOE
Column Interconnect
43

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