EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 21
![APEX 20K](/photos/39/63/396366/544-208-pqfp_sml.jpg)
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Manufacturer
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Figure 9. APEX 20K Interconnect Structure
Column
Interconnect
I/O
I/O
I/O
Row
Interconnect
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10
interconnect to drive LEs within MegaLAB structures.
MegaLAB
MegaLAB
MegaLAB
shows how the FastTrack Interconnect uses the local
I/O
I/O
APEX 20K Programmable Logic Device Family Data Sheet
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
MegaLAB
MegaLAB
MegaLAB
I/O
I/O
I/O
I/O
I/O
Column
Interconnect
21
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