EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 39
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Part Number
Manufacturer
Quantity
Price
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Figure 25. APEX 20K Bidirectional I/O Registers
Note to
(1)
or Local Interconnect
The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Row, Column,
Figure
25:
4 Dedicated
Inputs
Clock Inputs
2 Dedicated
2
Peripheral Control
Bus
12
OE[7..0]
VCC
CLK[1..0]
CLK[3..2]
ENA[5..0]
CLRn[1..0]
VCC
Input Pin to Input
Core to Output
Register Delay
VCC
VCC
Register Delay
VCC
VCC
VCC
APEX 20K Programmable Logic Device Family Data Sheet
Chip-Wide
Chip-Wide
Chip-Wide Reset
Input Pin to
Reset
Reset
Core Delay
Note (1)
Output Enable
Output Register
Chip-Wide
Input Register
OE Register
D
ENA
D
ENA
D
ENA
CLRN
CLRN
CLRN
Q
Q
Q
Open-Drain
Slew-Rate
Output
Control
Output Register
t
CO
Delay
VCCIO
Optional
PCI Clamp
39
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