MT47H256M8EB-25E:C Micron Technology Inc, MT47H256M8EB-25E:C Datasheet - Page 30

• Manufacturer Part Number: MT47H256M8EB-25E:C
• Description: 256MX8 DDR2 SDRAM PLASTIC GREEN FBGA 1.8V
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H256M8EB-25E:C

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-TFBGA
• Lead Free Status / Rohs Status: Compliant

Table 10: DDR2 I
Notes 1–7 apply to the entire table
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
Parameter/Condition
Burst refresh current:
mand at every
HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating; Data
bus inputs are floating
Operating bank interleave read current: All bank
interleaving reads, I
=
(I
CS# is HIGH between valid commands; Address bus in-
puts are stable during deselects; Data bus inputs are
switching (see Table 9 (page 28) for details)
DD
t
RCD (I
),
t
RRD =
DD
) - 1 x
t
RRD (I
t
RFC (I
t
CK (I
DD
DD
OUT
DD
Notes:
),
DD
Specifications and Conditions (Die Revision A) (Continued)
) interval; CKE is HIGH, CS# is
= 0mA; BL = 4, CL = CL (I
t
RCD =
t
);
CK =
t
CK =
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
CK (I
t
RCD (I
t
CK (I
UDQS#. I
operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
When
T
DD
DD
DD1
DD
C
C
DD
≤ 0°C
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
DD
DD
≥ 85°C
); refresh com-
= +1.8V ±0.1V, V
DD4R
),
); CKE is HIGH,
t
RC =
DD
, and I
values must be met with all combinations of EMR bits 10 and 11.
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
t
DD
IN
IN
RC
DD
DD
DD7
), AL
≤ V
≥ V
values must be derated (I
conditions:
IL(AC)max
IH(AC)min
require A12 in EMR1 to be enabled during testing.
DDQ
Symbol
REF
I
= +1.8V ±0.1V, V
I
I
I
DD6L
I
must be derated by 2%; and I
7%.
I
must be derated by 2%; I
slow must be derated by 30%; and I
80% (I
refresh option is still enabled).
30
DD5
DD6
DD7
DD2P
DD0
= V
Electrical Specifications – I
, I
DDQ
and I
DD1
DD6
/2
Configuration
, I
DD3P(SLOW)
will increase by this amount if T
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD2N
x4, x8, x16
C
x4, x8
x4, x8
≤ 85°C:
x16
x16
, I
DDL
DD2Q
DD
2Gb: x4, x8, x16 DDR2 SDRAM
= +1.8V ±0.1V, V
limits increase) on IT-option devices when
must be derated by 4%; I
, I
DD3N
DD2P
300
300
390
445
-25
, I
12
8
DD3P(FAST)
DD6
must be derated by 20%; I
-3E/-3 -37E
and I
280
280
340
395
12
© 2006 Micron Technology, Inc. All rights reserved.
8
DD6
REF
, I
DD7
= V
must be derated by
DD4R
260
260
295
355
DD
C
must be derated by
12
DDQ
8
< 85°C and the 2x
, I
DD4R
DD4W
Parameters
/2.
C
250
250
295
355
-5E
12
≤ +85°C.
8
and I
, and I
DD5W
Units
DD3P
DD5W
mA
mA
mA