DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 16

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
2.2.2
2.2.3
2.3
16
The degapped E1 output is emitted as NRZ data on TPOSD, or as HDB3 encoded data on TPOSD
and TNEGD. The dejittered and degapped output clock of each transmitter is emitted on TCLK at
the same frequency as the DTC input clock (TCLK clock is the ADPLL output). This working
mode is fully transparent - no data is lost or added in the transmission.
Retiming Mode
In the Retiming mode, the transmitter eliminates wander and jitter in the incoming clock (DTC).
Incoming E1 data is converted to a byte parallel format and fed into a two frame-wide elastic
buffer. The write and read control logic of this elastic store are initialized by the E1 frame
acquisition process. The data is read out of the elastic buffer using an external clock reference input
(DRETCKREF). DRETCKREF may or may not be at the same frequency as the DTC clock input.
If the read and write frequencies are different, the elastic store will periodically overflow or
underflow. In either case, the read control logic will process a controlled slip of one complete
frame in order to re-center the elastic buffer. This will result in the loss or repetition of one
complete E1 frame.
The retiming FIFO may also operate on an un-framed 2.048 Mbit/s signal busy setting the
transmitter to “Retiming Test Mode.” In this case, the read and write control logic of the elastic
store is in full free running mode and independent of the framing algorithm. As the data is
supposed to be un-framed in this test mode, CRC-4 error monitoring is not valid.
The output from the elastic buffer is converted to a serial format and emitted as NRZ data on
TPOSD, or output as HDB3 encoded data on TPOSD and TNEGD, at the TCLK clock rate that is
synchronous with the DRETCKREF clock input.
This working mode may be non-transparent. It can handle a maximum of 26 time slots (208 UI) of
wander or low frequency jitter before a frame slip occurs. This controlled frame slip assures that
the time-slot assignment is not lost at the output of the chip. All the jitter and wander due to the
multiplexing/demultiplexing process in the transmission is eliminated.
Pass-Through Mode
In the Pass-through mode no dejitter or retiming is performed on the input data.
The input clock (DTC) is shunted to the output clock (TCLK). CRC-4 monitoring and HDB3
encoding can be performed if so configured.
Receive Data Flow Description
The Receiver consists in eight fully independent E1 receiver blocks.
Each receiver input interface includes an NRZ encoded E1 signal input on RPOSDx or HDB3
encoded data on RPOSDx and RNEGDx, a serial clock RCLKx, and a Loss Of Signal (RLOSx)
alarm indication coming from the output of an E1 Line Interface Unit Receiver. The E1 input data
RPOSD/RNEGD may have a CRC-4 multiframe structure according to recommendation ITU
G.704 (refer to
microprocessor-accessible counters.
An AIS defect is detected according to recommendation ITU G.775 for the E1 incoming signal
after HDB3 decoding, and the corresponding alarm is accessible to the microprocessor.
Figure
5). HDB3 code errors (Bipolar Violations) are detected and stored in a set of
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