DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 51

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
RWB setup to active write
RWB hold from inactive write
CSB setup to active write
CSB hold from inactive write
DATA<7:0> setup to inactive write
DATA<7:0> hold from inactive write
Valid write pulse width
Inactive write to inactive INT (due to interrupt masking)
1. For non-multiplexed Address and Data bus (
2. For multiplexed Address and Data bus (
3. T is the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1)
Table 12. Microprocessor Data Write Timing Parameters
Parameter
AS
used as address latch enable)
AS
tied high)
Symbol
t
t
t
VWR
SRWB
HRWB
t
t
t
t
t
HCW
HDW
SCW
SDW
VWR
3
T + 6
Min
20
0
1
1
1
2
2
Typ
2*T + 21
Max
LXT6282
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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