DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 38

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.2.5
4.2.6
4.2.7
38
Bit 7:5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
XmtPosSlipEn
XmtNegSlipEn
XmtFifofAlmIntEn
XmtRetNOvrFlwEn
XmtRetPOvrFlwEn
XmtRbeOvrFlwEn
XmtCrcErrOvrFlwEn
XmtFasErrOvrFlwEn
Unused
XmtRmtAlmIntEn
XmtLomfIntEn
XmtOofIntEn
XmtAisDetIntEn
Unused
XMT_ALM_INTE0 - Transmitter Alarm Interrupt Enable 0 (i4H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel interrupt source.
The reset default is disabled (‘0’). All of the interrupt registers in the above section are capable of
activating the chip interrupt pin if their corresponding interrupt enable bits are set to 1.
XMT_ALM_INTE1 - Transmitter Alarm Interrupt Enable 1 (i5H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register can be used to enable an interrupt source for a particular E1 channel interrupt source.
The reset default is disabled (‘0’). All of the interrupt registers in the above section are capable of
activating the chip interrupt pin if their corresponding interrupt enable bits are set to 1.
XMT_FRMWD_ERC - Transmitter FrameWord Error Counter (i7- i6H)
(i = [0 to 7] and corresponds to the E1 channel number)
(i7H = bits <15:8>, i6H = bits <7:0>
This counter increments each time an errored E1 frameword (FAS and/or NFAS: see global
configuration register 0FH: bits CnfFeCnt[1..0]) is detected. A write to the MSByte of the counter
(register i7H) causes the entire counter to be buffered and then cleared. The contents of the buffer
can then be read.
Name
Name
Label
Label
R/W
R/W
R/W
R/W
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Datasheet
0
0
0
0
Default
Default
0
0
0
0
0
0
0
0