DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 37

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

4.2.4
Datasheet
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit <7:5>
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
XmtPosSlip
XmtNegSlip
XmtFifofAlm
XmtRetNegOvrFlw
XmtRetPosOvrFlw
XmtRbeOvrFlw
XmtCrc4ErrOvrFlw
XmtFasErrOvrFlw
Unused
XmtRmAlmSt
XmtLomfSt
XmtOofSt
XmtAisDetSt
Unused
XMT_ALM_STAT - Transmitter Alarm Status (i3H)
(i = [0 to 7] and corresponds to the E1 channel number)
This register gives the present status of each alarm source for a particular E1 channel transmitter.
These registers are associated with the interrupt source registers. Status the interrupt source bits
have an associated status bit. Generally, when an interrupt is being acknowledged, the status bit
will be checked to see the present status of the interrupt-generating source. Overflow event
interrupt sources do not have status bits.
Name
Name
Present status of Remote Alarm detect on DTDx input data.
0 - No Remote Alarm
1 - Remote Alarm
Present status of Out Of E1 CRC-4 MultiFrame detect on DTDx
input data.
0 - No LOMF
1 - LOMF
Present status of Out Of E1 Frame detect on DTDx input data.
0 - No OOF
1 - OOF
Present status of AIS defect detect on DTDx input data.
0 - No AIS defect
1 - AIS defect detected
Indicates that a positive frame slip has occurred in the retiming elastic
buffer. It is cleared when this register is read.
Indicates that a negative frame slip has occurred in the retiming elastic
buffer. It is cleared when this register is read.
Indicates that the transmit FIFO has overflowed (depending on the
OpCnf bits setting, this can be either the dejitter FIFO, or the retiming
elastic buffer). It is cleared when register is read.
This bit is set when the RetNegCnt[] retiming positive slip counter
rollover occurs. It is cleared when this register is read.
This bit is set when the RetPosCnt[] retiming positive slip counter
rollover occurs. It is cleared when this register is read.
This bit is set when the RbeCnt[] Remote Block error counter rollover
occurs. It is cleared when this register is read.
This bit is set when the Crc4ErrCnt[] error counter rollover occurs. It is
cleared when this register is read.
This bit is set when the FasErrCnt[] Frame Alignment Signal error
counter rollover occurs. It is cleared when this register is read.
Label
Label
Type
RO
RO
RO
RO
Type
RO
RO
RO
RO
RO
RO
RO
RO
LXT6282
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
37