DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 45
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DJLXT6282LE.A3
Manufacturer Part Number
DJLXT6282LE.A3
Description
Manufacturer
Intel
Datasheet
1.DJLXT6282LE.A3.pdf
(60 pages)
Specifications of DJLXT6282LE.A3
Lead Free Status / RoHS Status
Not Compliant
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4.3.10
Datasheet
Bit <15:10>
Bit <9:0>
Bit <15:0>
Bit
Bit
BpvCnt[15:0]
Unused
RcvRbeCnt[9:0]
This counter increments each time a remote CRC-4 block error is detected. A write to the MSByte
of the counter (Register jBH) causes the entire counter to be buffered and then cleared. The
contents of the buffer can then be read.
RCV_CD_ERC - Receiver Code Errors Counter (jDH)
(j =[8 to F] and corresponds to the E1 channel number)
(jDH = bits <15:8>, jCH = bits<7:0>)
This counter increments each time a code error (Bipolar Violation) is detected, according to
cnfBpvDet[1,0] configuration bits in global register 0FH. A write to the MSByte of the counter
(register jDH) causes the entire counter to be buffered and then cleared. The contents of the buffer
can then be read.
Name
Name
Label
Label
Type
RO
Type
RO
Default
Default
LXT6282
0
0
45
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