DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 48

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DJLXT6282LE.A3

Manufacturer Part Number
DJLXT6282LE.A3
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT6282LE.A3

Lead Free Status / RoHS Status
Not Compliant
LXT6282
48
RCLKi (with CnfRxClkIn = 1
Conf. Register @ 0xAF / bit #5)
RCLKi (with CnfRxClkIn = 0
Conf. Register @ 0xAF /bit #5)
MTCi
MTDi
Global Conf. Register @ AFH / bit #4 :
DTDi setup time to DTCi falling/rising edge
DTDi hold time from DTCi falling/rising edge
RCLKi rising/falling edge to MTCi rising/falling edge
MTCi falling/rising edge to MTDi
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
2. Considering outputs with a 25pF load
1. i = [0 to 7] and corresponds to the eight different E1 channel numbers
2. Considering outputs with a 25pF load
Global Conf. Register @ 0xAF / bit #7 :
DTCi
DTDi
Figure 8. E1 inputs, received from the demultiplexer, Timing
Table 9.
Figure 9. E1 outputs, transmitted to the multiplexer, Timing
Table 10. E1 outputs, transmitted to the multiplexer, Timing
t
RCKOpd
E1 inputs, received from the demultiplexer, Timing Parameters
t
RDOpd
t
RDIsu
Parameter
Parameter
t
RDIh
CnfRxClkOut = 0
CnfTxClkIn = 0
Symbol
t
RCKOpd
t
RDOpd
t
Symbol
RCKOpd
t
t
t
RDOpd
RDIsu
RDIh
t
RDIsu
Min
3
1
Min
1
3
Typ
t
RDIh
CnfTxClkIn = 1
Typ
CnfRxClkOut = 1
Max
12
7
Max
Datasheet
GIBRALTAR
ns
ns
_
Unit
DS
ns
ns
DRAWING
_
R
Unit
1.0.
FM
1 - 3/1/99
- 6/15/98

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