DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 30

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.1
4.1.1
30
j9-j8H
jB-jAH
jD-jCH
Bit
<7:6>
Address
Bit
CnfBpvIns[1..0]
REC_BLCK_ERC
REC_RMT_BLCK_ERC
REC-CD_ERC
Name
Global Registers
The registers described in this section are related to global configuration, tests and alarms.
GLOB_CONF0 - Global Operational Configuration 0 (0FH)
Configures high level operational characteristics of the chip.
Mnemonic
These bits configure the code errors (Bipolar Violation) inserted in all the
E1 HDB3 transmitter outputs (TPOSD and TNEGD, to the LIU) when the
BpvInsert is enabled (see register iEH) - (used for testing)
00 - Insert a single code error
01 - Insert one code error per second (used for testing)
10 - Insert one code error per multiframe (used for testing)
11 - Insert one code error per 1000 bits (BER 10-3) (used for testing)
Receiver CRC-4 Block Error Counter
Receiver Remote CRC-4 Block Error Counter
Receiver Code Errors Counter
Label
Register Name
Type
R/W
Type
R
R
R
Datasheet
Default
Page #
0
41
40
41