DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 26

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
3.1.10.7
3.1.11
3.1.11.1
26
Output Interface
NRZ receive data and clock are emitted on MTDx and MTCx pins. MTCx clock is synchronous
with an RCLKx input clock or DRETCKREF blue clock if AIS is inserted in the receiver or if in
Autotest Mode. The relative phase between output data and clock can be configured via the
microprocessor (MTDx data outputs emitted on the rising or falling edge of the output clock
MTCx: see global register AFH).
Test Pattern Generator for Autotesting/Maintenance
CRC-4 E1 Framed Test Pattern
An internal E1 framed pattern generator may be enabled via the microprocessor for autotesting and
maintenance purposes. The sequence consists of an E1 CRC-4 framed signal with the FAS, NFAS,
MFAS and CRC-4 bits in the time slots 0 and a PRBS 2E15-1 sequence in the time slots 1 ->31.
If enabled (see registers 1FH and jEH), the E1 framed test pattern sequence is sent to the receiver
input and then emitted on MTD data output pin, with the associated DRETCKREF blue clock
emitted on MTC clock output pin. So, by looping back externally, the MTC/MTD output signals to
the DTC/DTD input signals, the chip can be autotested without any external test equipment.
PRBS Unframed Test Pattern
If enabled (see registers 1FH and jEH), the internal test pattern generator can also generate the
standard pseudo-random (2E15-1 sequence) unframed test signal used for E1 jitter analysis
(Recommendation ITU-T O171) emitted on MTD data output pin, with the associated
DRETCKREF blue clock emitted on MTC clock output pin.
MICROCONTROLLER INTERFACE
This section contains a description of the asynchronous microprocessor interface. A
microprocessor should be connected to the LXT6282 for reading and writing data via the
microprocessor interface pins.
The microprocessor interface is a generic asynchronous interface, including an address bus (A
[7..0]), data bus (DATA [7..0]) and handshaking pins (WRB/RWB, RDB/E, CSB, and ALE). The
MCUTYPE input pin indicates the type of microprocessor interface to be used – Intel or Motorola.
There is also an INT output pin that indicates status changes to the microprocessor.
This interface has the same features as Intel’s LXT6051 and LXT6251A chips.
Intel Interface
The Intel interface is indicated by driving the MCUTYPE input pin LOW. It uses the WRB/RWB
input pin as WRB and the RDB/E input pin as RDB.
A read cycle is indicated to the LXT6282 by the uP forcing a LOW on the RDB pin with the WRB
pin held HIGH.
A write cycle is indicated to the LXT6282 by the uP forcing a LOW on the WRB pin with the RDB
pin held HIGH.
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