DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 4

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
5.0
6.0
7.0
8.0
4
4.2
4.3
Test Specifications
Testability
6.1
Glossary
Package Information
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
Transmit Side Registers ...................................................................................... 34
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10 XMT_RETMBUF - Transmitter Retiming Buffer Positive & Negative
4.2.11 XMT_RTMBUF_STAT - Transmitter Retiming Buffer Status (iDH)........ 40
Receive Side Registers....................................................................................... 40
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10 RCV_CD_ERC - Receiver Code Errors Counter (jDH) .......................... 45
IEEE 1149.1 Boundary Scan Description ........................................................... 52
6.1.1
6.1.2
....................................................................................................................... 59
.................................................................................................................... 52
CHIP_ID_NMB - Chip ID Number (4FH) ................................................ 32
BUFF_ALLCNT - Buffer All Counters (5FH)........................................... 33
E1_RCV_AISTAT - E1 Receivers AIS Status (8FH) .............................. 33
EI_XMT_AISTAT - E1 Transmitters AIS Status (9FH) ........................... 33
GLOB_CONF - Global Operational Configuration 3 (AFH) .................... 34
XMT_CONF - Transmitter Configuration (iEH)....................................... 35
XMT_ALRM_INTO - Transmitter Alarm Interrupt 0 (i1H) ....................... 36
XMT_ALRM_INT1 - Transmitter Alarm Interrupt 1(i2H) ......................... 36
XMT_ALM_STAT - Transmitter Alarm Status (i3H) ............................... 37
XMT_ALM_INTE0 - Transmitter Alarm Interrupt Enable 0 (i4H) ............ 38
XMT_ALM_INTE1 - Transmitter Alarm Interrupt Enable 1 (i5H) ............ 38
XMT_FRMWD_ERC - Transmitter FrameWord Error Counter (i7- i6H) 38
XMT_BLCK_ERC - Transmitter CRC-4 Block Errors Counter
(i9H - i8H) ............................................................................................... 39
XMT_RMT_ERC - Transmitter Remote CRC-4 Block Errors Counter
(iB - iAH)................................................................................................. 39
Slip Counters (iCH) ................................................................................ 39
RCV_CONF- Receiver Configuration (jEH)............................................ 41
RCV_ALRM_INT0 - Receiver Alarm Interrupt 0 (j1H) ............................ 42
RCV_ALRM_INT1 - Receiver Alarm Interrupt 1 (j2H) ............................ 42
REC_ALRMS - Receiver Alarm Status (j3H).......................................... 42
RCE_ALM_INTE0 - Receiver Alarm Interrupt Enable Register 0 (j4H).. 43
RCV_ALM_INTE1 - Receiver Alarm Interrupt Enable Register 1 (j5H).. 43
RCV_FRMWD_ERC - Receiver FrameWord Error Counter (j7 - j6H) ... 44
RCV_BLCK_ERC - Receiver CRC-4 Block Error Counter (j9 - j8H) ...... 44
RCV_RMT_BLCK_ERC - Receiver Remote CRC-4 Block Error Counter
(jB - jAH)................................................................................................. 44
Instruction Register and Definitions........................................................ 53
6.1.1.1 EXTEST (‘b00) .......................................................................... 53
6.1.1.2 SAMPLE/PRELOAD (‘b01) ....................................................... 53
6.1.1.3 BYPASS (‘b11).......................................................................... 53
6.1.1.4 IDCODE (‘b10) .......................................................................... 54
Boundary Scan Register ........................................................................ 54
.................................................................................................. 46
............................................................................................... 60
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