DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 21

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
If the read system clock (DRETCKREF) frequency is lower than the write incoming clock (DTCx)
frequency, then when the FIFO is close to overflow, the read control logic will perform a slip of
one complete frame. This results in the loss of the last received frame (“negative slip”).
Positive and negative slips in the elastic store are indicated via two maskable interrupts, and
counted in two different 4-bit counters accessible via the microprocessor. A maskable interrupt is
provided to indicate counter overflows.
For FIFO and Wander monitoring, or delay calculation, the relative difference between FIFO write
and read pointers is indicated in register iCH (6 bits used), accessible via the microprocessor.
For testing and debugging, this two-frame-wide elastic buffer may be reset via the microprocessor
to its center point (see register iEH).
Datasheet
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