DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 24

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
3.1.10
3.1.10.1
3.1.10.2
24
Retiming Mode (No AIS or AIS)
Dejitter Mode (No AIS)
Dejitter Mode (AIS insert)
Pass Through Mode (No AIS)
Pass Through Mode (AIS insert)
Table 3.
TCLK clock sources
The relative phase between output data and clock can be configured via microprocessor (TPOSDx/
TNEGDx data outputs emitted on rising or falling edge of the output clock TCLKx: see global
register AFH).
Depending on the transmitter configuration, TCLK transmit clock output may be provided by
different sources:
Transmitter clock output scheme
Receiver Operation
Line decoding HDB3
The HDB3 decoder is microprocessor selectable. When selected, this block accepts an HDB3
encoded E1 signal via data inputs RPOSDx and RNEGDx and clock RCLKx. A bipolar violation
(or code error) detector is implemented in the HDB3 decoder. The Bipolar Violation (BPV) Errors
Detector can be configured for all the E1 HDB3 receivers via the microprocessor. The detector can:
BPV errors are accumulated in a 16-bit counter that can be read by the microprocessor. A maskable
interrupt is provided to indicate counter overflows.
If the HDB3 decoder is not used, the E1 NRZ data is input on RPOSD. In this case, RNEGD input
pin has to be grounded, and the BPV error detection is invalid.
The relative phase between E1 data (on RPOSDx/RNEGDx pins) and clock (on RCLKx pin)
inputs can be configured via microprocessor (RPOSDx/RNEGDx data inputs may be sampled, in
the transmitter, by rising or falling edge of the input clock RCLKx: see global register AFH).
AIS Detection
After HDB3 decoding, an AIS detection is performed on the incoming data according to
recommendation ITU G.775.
AIS defect alarm is declared when each of two consecutive double frame periods (512 bits) has two
or less ZEROs, and the alarm is cleared when three or more ZEROs or when the Frame Alignment
Signal has been found in each of two consecutive double frame periods.
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be disabled
detect two consecutive ‘1’s’ with the same polarity (except when it is used as part of a valid
HDB3 substitution)
detect BPV that do not alternate polarity (recommendation ITU O161)
detect two consecutive ‘1’ with the same polarity, or BPV that do not alternate polarity, or four
consecutive ‘0’ badly encoded.
DRETCKREF input
DTC input
DPLLCKREF input/32
DTC input
DRETCKREF input
Synchronous with
DRETCKREF
ADPLL filtered output
DPLLCKREF/32
DTC
DRETCKREF
Clock source
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