DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 17

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
If the Loss Of Signal alarm is active, the receiver may insert an AIS signal (all ones in the data),
using the DRETCLK clock reference input as a blue clock.
Data is fed to the framing/multiframing block that synchronizes the Receiver Timing Generator to
the incoming E1 data frame, and provides Out Of Frame (OOF) and Out Of Multiframe (OOMF)
alarm indications. Once the frame synchronization is acquired, frame word errors are detected,
counted and stored in a set of microprocessor accessible counters. Remote End Block Errors
(REBE) are also counted and stored in a set of microprocessor-accessible counters. The Remote
alarm is monitored (but not inserted) for status changes.
A CRC-4 calculation is also performed over the multiframe and compared to the incoming CRC-4
value. Again, any errors are counted and stored in a set of microprocessor- accessible counters.
The E1 signal is emitted as NRZ data on MTD and clock on MTC.
All the AIS, framing, multiframing and CRC-4 monitoring functions can be independently
bypassed in each receiver if not needed.
For testing and maintenance purposes, the receiver can be set via the microprocessor as a sequence
pattern generator on MTD and MTC data and clock output pins (framed or unframed PRBS
sequence).
Datasheet
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