PIC16F724-E/MV Microchip Technology, PIC16F724-E/MV Datasheet - Page 145

• Manufacturer Part Number: PIC16F724-E/MV
• Description: 7KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI, A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F724-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, AUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: -
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

16.0
The
Asynchronous
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 16-1:
© 2009 Microchip Technology Inc.
Baud Rate Generator
Addressable
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
and
SPBRG
Receiver
personal
+ 1
AUSART TRANSMIT BLOCK DIAGRAM
F
Multiplier
OSC
Universal
SYNC
BRGH
computers.
Transmitter
TXEN
÷ n
x4
1
x
n
x16 x64
0
1
Synchronous
Half-Duplex
(AUSART)
0
0
MSb
(8)
Transmit Shift Register (TSR)
PIC16F72X/PIC16LF72X
TX9D
TXREG Register
• • •
TX9
The AUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Sleep operation
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
8
Data Bus
TRMT
LSb
0
TXIF
TXIE
Pin Buffer
and Control
SPEN
DS41341E-page 145
Interrupt
TX/CK