PIC16F724-E/MV Microchip Technology, PIC16F724-E/MV Datasheet - Page 180

• Manufacturer Part Number: PIC16F724-E/MV
• Description: 7KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI, A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F724-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 7 KB
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, AUSART
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: -
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16F72X/PIC16LF72X
17.2.5
When the R/W bit of the received address byte is clear,
the master will write data to the slave. If an address
match occurs, the received address is loaded into the
SSPBUF register. An address byte overflow will occur
if that loaded address is not read from the SSPBUF
before the next complete byte is received.
An SSP interrupt is generated for each data transfer byte.
The BF, R/W and D/A bits of the SSPSTAT register are
used to determine the status of the last received byte.
FIGURE 17-10:
DS41341E-page 180
SDA
SCL
SSPIF
BF
SSPOV
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
3
I
4
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
7
R/W = 0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
© 2009 Microchip Technology Inc.
ACK is not sent.
D3
5
D2
6
D1
7
D0
8
ACK
9
condition
Bus Master
sends Stop
P