HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 144

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.11.5
3.8.11.6
Intel
Datasheet
144
®
5100 Memory Controller Hub Chipset
PEXDEVSTS[7:2,0] - PCI Express* Device Status Register
The PCI Express* Device Status register provides information about PCI Express*
device specific parameters associated with this port.
PEXLNKCAP[7:2,0] - PCI Express* Link Capabilities Register
The Link Capabilities register identifies the PCI Express* specific link capabilities.
Device:
Function:
Offset:
15:6
Bit
5
4
3
2
1
0
RWC
RWC
RWC
RWC
Attr
RO
RO
RV
7-2, 0
0
76h
Default
000h
0
0
0
0
0
0
Reserved.
TP: Transactions Pending
1: Indicates that the PCI Express* port has issued Non-Posted Requests which
have not been completed.
0: A device reports this bit cleared only when all Completions for any
outstanding Non-Posted Requests have been received.
Since the MCH Root port that do not issue Non-Posted Requests on their own
behalf, it is hardwired to 0b.
APD: AUX Power Detected
1- AUX power is detected by the PCI Express* port.
0: No AUX power is detected
URD: Unsupported Request Detected
This bit indicates that the device received an Unsupported Request in the PCI
Express* port. Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control Register.
0: No Unsupported Request detected at the port
1: Unsupported Request detected at the port
This records the detection of receiving an unsupported request, error IO2.
FED: Fatal Error Detected
This bit indicates that status of a fatal (uncorrectable) error detected in the
PCI Express* port. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
1: Fatal errors detected
0: No Fatal errors detected
NFED: Non Fatal Error Detected
This bit indicates status of non-fatal errors detected. This bit gets set if a non-
fatal uncorrectable error is detected in the PCI Express* port. Errors are
logged in this register regardless of whether error reporting is enabled or not
in the Device Control register.
1: Non-Fatal Errors detected
0: No Non-Fatal Errors detected
CED: Correctable Error Detected
This bit indicates status of correctable errors detected. This bit gets set if a
correctable error is detected in the PCI Express* port. Errors are logged in this
register regardless of whether error reporting is enabled or not in the PCI
Express* Device Control register.
1: Correctable errors detected
0: No correctable errors detected
Intel
®
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009