HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 74

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 30.
3.5.2
Table 31.
3.6
Table 32.
Intel
Datasheet
74
®
5100 Memory Controller Hub Chipset
I/O Address: CF8h
CFGDAT: Configuration Data Register
CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This
register is only accessed if there is an access to I/O address, CFCh on the processor bus
and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O
access define how many configuration bytes are accessed.
I/O Address: CFCh
Intel
Mapped Registers
These registers are mapped into the fixed chipset specific range located from FE60
0000h - FE6F FFFFh. These appear at fixed addresses to support the boot process.
These registers also appear in the regular PCI Express* configuration space.
Table 32, “Mapping for Fixed Memory Mapped Registers”
of the registers in this region.
Mapping for Fixed Memory Mapped Registers (Sheet 1 of 2)
BOFL0
BOFL1
BOFL2
BOFL3
SPAD0
SPAD1
30:24
23:16
15:11
10:8
31:0
7:2
1:0
Bit
Bit
31
Register
®
Attr
Attr
RW
RW
RW
RW
RW
RW
RW
RV
5100 Memory Controller Hub Chipset Fixed Memory
Default
FE60_C000
FE60_C400
FE60_C800
FE60_CC00
FE60_D000
FE60_D400
Default
0h
0h
0h
0h
0h
0h
0h
0
Memory Address
Configuration Data Window
The data written or read to the configuration register (if any) specified by
CFGADR
CFGE: Configuration Enable
Unless this bit is set, accesses to the CFGDAT register will not produce a
configuration access, but will be treated as other I/O accesses. This bit is
strictly an enable for the CFC/CF8 access mechanism and is not forwarded to
ESI or PCI Express*.
Reserved.
Bus Number
If 0, the MCH examines device to determine where to route. If non-zero, route
as per PBUSN and SBUSN registers.
Device Number
This field is used to select one of the 32 possible devices per bus.
Function Number
This field is used to select the function of a locally addressed register.
Register Offset
If this register specifies an access to MCH registers, this field specifies a group
of four bytes to be addressed. The bytes accessed are defined by the Byte
enables of the CFGDAT register access
Writes to these bits have no effect, reads return 0
Intel
®
Description
Description
5100 MCH Chipset—Register Description
defines the memory address
Order Number: 318378-005US
July 2009