HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 68
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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Intel
Datasheet
68
®
5100 Memory Controller Hub Chipset
• Device 16: Device 16, Function 0 is routed to the Front Side Bus (FSB) Controller,
• Device 17: Reserved. These devices reside at DID 65F1h.
• Device 19: Device 19, Function 0 is routed to Miscellaneous registers. These
• Device 21: Device 21, Function 0, Channel 0 Memory Map, Error Flag/Mask, and
• Device 22: Device 22, Function 0, Channel 1 Memory Map, Error Flag/Mask, and
the DMA channels. Device 8, Function 1 contains the MMIO space configuration
registers. The DMA Engine controller resides at DID 65FFh.
Interrupt and System Address registers. Function 1 is routed to the Front Side Bus
Address Mapping, Memory Control, and Error registers. Function 2 is routed to FSB
Error Registers. These devices reside at DID 65F0h.
devices reside at DID 65F3h.
Channel Control registers. These devices reside at DID 65F5h.
Channel 1 Control registers. These devices reside at DID 65F6h.
Intel
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009
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