HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 349

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.20.3
Table 111.
5.20.3.1
Note:
July 2009
Order Number: 318378-005US
For further clarification, here is an example scenario of a case in which a change to the
recommended timeout is required. In this scenario, a video card is unable to respond
within the recommended timeout. Furthermore, the default Microsoft Windows* driver
maps the video frame buffer in MMIO space as Uncacheable Speculative Write
Combining (USWC) memory. The CPU may speculatively execute a load (read) to the
frame buffer region. The video controller may be unable to respond to the speculative
read and could issue a retry. The system will continue to reissue the load to the video
controller which may respond back with a retry. After 20 ms, the Intel
Chipset timer expires and generates an NMI followed by a Microsoft Windows* blue
screen. To work around this problem, set the PEXGCTRL Completion Timeout to a
maximum value of 3FFFh. The PEXGCTRL timeout should be set to ‘744h’ for any
SMBus transactions through the Intel
device outside of the Intel
completed, the PEXGCTRL timeout should be set back to the maximum value of 3FFFh.
Ensure that the system is silent on the PCI Express* side before changing the timer
value (3FFFh to 744h and vice versa).
SMBus Transaction Field Definitions
The SMBus target port has it’s own set of fields which the MCH sets when receiving an
SMBus transaction. They are not directly accessible by any means for any device.
SMBus Transaction Field Summary
Table 111, “SMBus Transaction Field Summary”
presented on the SMBus following the byte address of the MCH itself. Note that the
fields can take on different meanings depending on whether it is a configuration or
memory-mapped access type. The command indicates how to interpret the bytes.
Command Field
The command field indicates the type and size of transfer. All configuration accesses
from the SMBus port are initiated by this field. While a command is in progress, all
future writes or reads will be negative acknowledged (NAK) by the MCH to avoid having
registers overwritten while in use. The two command size fields allows more flexibility
on how the data payload is transferred, both internally and externally. The begin and
end bits support the breaking of the transaction up into smaller transfers, by defining
the start and finish of an overall transfer.
Packet Error Code (PEC) is not a supported feature as indicated in bit [4] below.
Position
10
11
1
2
3
4
5
6
7
8
9
Mnemonic
®
BYTCNT
ADDR3
ADDR2
ADDR1
ADDR0
5100 MCH Chipset
DATA3
DATA2
DATA1
DATA0
CMD
STS
Command
Byte Count
Bus Number (Register Mode) or Destination Memory (Memory Mapped Mode)
Device/Function Number (Register Mode) or Address Offset [23:16] (Memory
Mapped Mode)
Extended Register Number (Register Mode) or Address Offset [15:8] (Memory
Mapped Mode)
Register Number (Register Mode) or Address Offset [7:0] (Memory Mapped Mode)
Fourth Data Byte [31:24]
Third Data Byte [23:16]
Second Data Byte [15:8]
First Data Byte [7:0]
Status, only for reads
®
5100 MCH Chipset. Once the SMBus transactions are
®
5100 MCH Chipset targeting a PCI Express*
indicates the sequence of data as it is
Field Name
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
349