HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 243

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.22.7
Note:
3.11.22.8
3.11.22.9
July 2009
Order Number: 318378-005US
INTRDELAY - Interrupt Delay Register
The Interrupt Delay Time field specifies how long the chipset will delay the interrupt
signal to the CPU in order to coalesce interrupts. The setting of INTRCTRL:Interrupt
Interrupt Enable to 1 causes a timer to start for period equal to Interrupt Delay Time
(±5%), which masks the interrupt generation until the timer expires. When the timer
expires, if any interrupts are pending (i.e., INTRCTRL:Interrupt bit is 1), then the
chipset generates an interrupt to the CPU. If an interrupt occurs after the time expires,
then the chipset immediately generates the interrupt to the CPU. The state of the timer
does not effect the value of the bits in the INTRCTRL register.
A change to the Interrupt Delay Time field does not take effect until after the next time
Master Interrupt Enable is set (i.e., writing INTRDELAY does not modify a timing cycle
in progress). When software writes INTRCTRL with Master Interrupt Enable = 1,
regardless of the previous value of that bit, the chipset starts the timer (if it is not
running) or restarts the timer (if it is already running) using the current value from the
Interrupt Delay Time register. Thus, interrupts will be delayed for Interrupt Delay Time
µs after each write to the INTRCTRL register.
The interrupt delay timer has no effect on the MCH and interrupts will be enabled as
soon as the Master Interrupt Enable bit in the INTRCTRL bit is set and there are
pending interrupts.
CS_STATUS: Chipset Status Register
The CS_STATUS register provides the means for the chipset to report conditions that
might be adverse to DMA Engine operation.
CHAN_SYSERR_MSK[3:0]: Channel System Error Mask Register
The Channel System Error Mask Register
may cause SERR, SCI/NMI through BIOS control via ERR[2:0]# pins in the Intel
MCH Chipset. If one of the bits in the CHAN_SYSERR_MSK register is set, then that
Offset:
Offset:
13:0
15:2
Bit
Bit
15
14
1
0
Attr
Attr
RW
RO
RO
RO
RO
RO
®
5100 MCH Chipset
0Ch
0Eh
Default
Default
0h
0
0
0
0
0
Interrupt Coalescing Supported
The MCH doe not support interrupt coalescing by delaying interrupt generation.
Reserved
Interrupt Delay Time
Specifies the number of µs that the chipset delays generation of an interrupt
(legacy or MSI) from the time that interrupts are enabled (i.e., Master Interrupt
Enable bit in the INTRCTRL bit is set). The MCH does not support interrupt delay
timer and hence hardwired to 0.
Reserved
MMIO_Rstn: MMIO Restriction
when this bit is zero, it indicates the DMA can access all MMIO space. There is no
limitation in the Intel
Deg_Mode: Degraded Mode
The Intel
operation and is hardwired to 0.
®
5100 MCH Chipset does not support degraded mode for DMA Engine
®
5100 MCH Chipset address decoding logic.
1
provides selective control to mask errors that
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
®
Datasheet
5100
243