HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 333

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.17.2.1
5.17.2.2
5.17.3
5.17.3.1
Table 106.
5.17.3.2
July 2009
Order Number: 318378-005US
Bus
Number
Device
Number
Function
Number
Tag
Field
Specifies the bus number that
the requester resides on.
Specifies the device number of
the requester.
Specifies the function number
of the requester.
Identifies a unique identifier
for every transaction that
requires a completion. Since
the PCI Express* ordering
rules allow read requests to
pass other read requests, this
field is used to reorder
separate completions if they
return from the target out-of-
order.
Unsupported Messages
If the Intel
Table 102, “Incoming PCI Express*
as specified in the Vendor defined message section of the PCI Express* Base
Specification, Rev. 1.0a.
32/64-bit Addressing
For inbound and outbound writes and reads, the MCH supports 64-bit address format.
If an outbound transaction’s address is a 32-bit address, the MCH will issue the
transaction with a 32-bit addressing format on PCI Express*. Only when the address
requires more than 32 bits will the MCH initiate transactions with 64-bit addressing
format. It is the responsibility of the software to ensure that the relevant bits are
programmed for 64 bits based on the OS limits. (e.g., 36 bits for MCH)
Transaction Descriptor
The PCI Express* Base Specification, Rev. 1.0a defines a field in the header called the
Transaction Descriptor. This descriptor comprises three sub-fields:
Transaction ID
The Transaction ID uniquely identifies every transaction in the system. The Transaction
ID comprises four sub-fields described in
PCI Express* Transaction ID Handling
Attributes
PCI Express* supports two attribute hints described in
• Vendor Type 0 - Unsupported Request
• Vendor Type 1 - Drop request.
• Transaction ID
• Attributes
• Virtual Channel ID
Definition
®
®
5100 MCH Chipset
5100 MCH Chipset decodes any vendor message (which is not defined in
The MCH sets this field to 0.
The MCH fills this field in with
the content of the DID register
for this port.
The MCH sets this field to 0.
The MCH fills this field in with a
value such that every pending
request carries a unique Tag.
MCH as Requester
Requests”), the MCH will take the following actions
Table
106.
The MCH preserves
this field from the
request and copies it
to the completion.
MCH as Completer
Intel
Table
®
5100 Memory Controller Hub Chipset
107.
For peer-to-peer posted
requests, the MCH
preserves these fields
from the source PCI
Express* port to the
destination port.
For peer-to-peer non-
posted requests, the
MCH preserves
Requestor ID Bus,
Device, and Function,
but reassigns the Tag.
Peer-to-peer
Transaction
Datasheet
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