HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 392

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 139.
7.1.8
Figure 60.
Intel
Datasheet
392
®
5100 Memory Controller Hub Chipset
Public TAP Instructions
Public Data Instructions
This section describes the data registers that are accessed by the public and private
instructions. Data shifts into all chains through the MSB of the data register as shown in
Figure 60, “TAP Data Register”
TAP Data Register
BYPASS
EXTEST
SAMPLE/
PRELOAD
IDCODE
CLAMP
HIGHZ
Instruction
Encoding
11111111
00000000
00000001
0000010
0000100
0001000
Data Register
Boundary Scan
Boundary Scan
Boundary Scan
IDCODE
Bypass
Bypass
Selected
which is the same as the instruction register.
The BYPASS command selects the Bypass register, a single bit
register connected between the TDI and TDO pins. This allows
more rapid movement of test data to and from other
components in the system.
The EXTEST instruction allows circuitry or wiring external to the
devices to be tested. Boundary Scan register cells at outputs are
used to apply stimulus, while Boundary Scan register cells at
inputs are used to capture data.
The SAMPLE/PRELOAD instruction is used to allow scanning of
the Boundary Scan register without causing interference to the
normal operation of the device. Two functions can be performed
by use of the SAMPLE/PRELOAD instruction:
1.
2.
The IDCODE instruction is forced into the parallel output latches
of the instruction register during the Test-Logic-Tap state. This
allows the Device Identification register to be selected by
manipulation of the broadcast TMS and TCK signals for testing
purposes, as well as by a conventional instruction register scan
operation.
This allows static “guarding” values to be set into components
that are not specifically being tested while maintaining the
Bypass register as the serial path through the device.
The HIGHZ instruction is used to force all outputs of the device
(except TDO) into a high impedance state. This instruction shall
select the Bypass register to be connected between TDI and TDO
in the Shift-DR controller state.
SAMPLE allows a snapshot of the data flowing into and
out of the device to be taken without affecting the
normal operation of the device.
PRELOAD allows an initial pattern to be placed into the
Boundary Scan register cells. This allows initial known
data to be present prior to the selection of another
Boundary Scan test operation.
Intel
Description
®
5100 MCH Chipset—Testability
Order Number: 318378-005US
July 2009