HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 43

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 6.
July 2009
Order Number: 318378-005US
Processor Front Side Bus 1 Signals (Sheet 4 of 4)
FSB1LOCK#
FSB1MCERR#
FSB1REQ[4:0]#
FSB1RESET#
FSB1RS[2:0]#
FSB1RSP#
FSB1TRDY#
FSB1VREF
Signal Name
®
5100 MCH Chipset
I
I/O
I/O
O
O
O
O
Analog
Type
Processor 1 Lock:
FSB1LOCK# indicates to the system that a transaction must occur atomically.
For a locked sequence of transactions, FSB1LOCK# is asserted from the
beginning of the first transaction to the end of the last transaction.
When the priority agent asserts FSB1BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes FSB1LOCK# deasserted. This
enables symmetric agents to retain ownership of the processor FSB throughout
the bus locked operation and ensure the atomicity of lock.
Processor 1 Machine Check Error:
FSB1MCERR# is asserted to indicate an unrecoverable error without a bus
protocol violation. It may be driven by all processor FSB agents.
FSB1MCERR# assertion conditions are configurable at a system level. For more
details regarding machine check architecture, refer to the Intel
Architectures Software Developer’s Manual, Volume 3: System Programming
Guide.
Processor 1 Bus Request Command:
FSB1REQ[4:0]# define the attributes of the request. FSB1REQ[4:0]# are
transferred at 2x rate and are source synchronous to FSB1ADSTB[1:0]#. They
are asserted by the requesting agent during both halves of request phase. In
the first half, the signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second half the signals carry
additional information to define the complete transaction type. Refer to the
FSB1AP[1:0]# signal description for details on parity checking of these signals.
Processor 1 Reset:
FSB1RESET# is an output from the MCH. The MCH asserts FSB1RESET# while
RESETI# (PLTRST# from ICH9R) is asserted and for approximately 1 ms after
RESETI# is deasserted. The FSB1RESET# allows the processors to begin
execution in a known state and invalidates their internal caches without writing
back any of their contents.
Processor 1 Response Status Signals:
FSB1RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction). FSB1RS[2:0]# indicate
the type of response according to the following:
Processor 1 Response Status Parity:
FSB1RSP# provides parity protection for the FSB1RS[2:0] signals. Driven
during assertion of FSB1RS[2:0]# as required for the agent responsible for
completion of the current transaction. A correct parity signal is high if an even
number of covered signals are low and low if an odd number of covered signals
are low. When FSB1RS[2:0]# = 000 or idle is indicated, FSB1RSP# is high.
Processor Bus 1 Target Ready:
FSB1TRDY# (Target Ready) is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer, the target of the processor
transaction is able to enter the data transfer phase.
Processor 1 Voltage Reference:
FSB1VREF is Processor 1 voltage reference. Refer to the Quad-Core and Dual-
Core Intel
Controller Hub Chipset for Communications, Embedded, and Storage
Applications – Platform Design Guide or Intel
and SL9400 and Intel
Communications and Embedded Applications – Platform Design Guide for the
voltage value.
Encoding
000
001
010
011
100
101
110
111
®
Xeon
Response Type
Idle state
Retry response
Deferred response
Reserved (not driven by MCH)
Hard Failure (not driven by MCH)
No data response
Implicit Writeback
Normal data response
®
Processor 5000 Sequence with Intel
®
5100 Memory Controller Hub Chipset for
Description
Intel
®
5100 Memory Controller Hub Chipset
®
Core™2 Duo Processors T9400
®
5100 Memory
®
64 and IA-32
Datasheet
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