HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 228

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.11
3.11.12
Intel
Datasheet
228
®
5100 Memory Controller Hub Chipset
MSINXPTR - Message Signaled Interrupt Next Pointer Register
MSICTRL - Message Signaled Interrupt Control Register
Device:
Function:
Offset:
7:0
Device:
Function:
Offset:
15:8
7
6:4
3:1
0
Bit
Bit
RO
RO
RO
RW
RO
RW
Attr
Attr
8
0
59h
8
0
5Ah
6Ch
0h
0
000
0h
0
Default
Default
NXTPTR: MSI Next Pointer: The DMA Engine device is implemented as a PCI
Express* device and this points to the PCI Express* capability structure.
Reserved
AD64CAP: 64-bit Address Capable
All processors used with the Intel
addressing, hence this is hardwired to 0
MMEN: Multiple Message Enable
Software initializes this to indicate the number of allocate messages which is
aligned to a power of two. When MSI is enabled, the software will allocate at least
one message to the device. See
Interrupt Data Register”
MMCAP: Multiple Message Capable
The Intel
(power of two) for handling
MSIEN: MSI Enable
This bit enables MSI as the interrupt mode of operation instead of the legacy
interrupt mechanism.
0: Disables MSI from being generated.
1: Enables MSI messages to be generated for DMA related interrupts.
An extract of the flowchart of the DMA Engine error handling is given in
“Intel® 5100 Memory Controller Hub Chipset DMA Error/Channel Completion
Interrupt Handling Flow.”
• DMA errors
• DMA completions
®
5100 MCH Chipset DMA Engine supports only one interrupt message
below for discussion on how the interrupts are handled.
Intel
Section 3.11.14, “MSIDR: Message Signaled
®
Description
Description
5100 MCH Chipset do not support 64-bit
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
Figure 14,
July 2009