HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 94

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
94
®
5100 Memory Controller Hub Chipset
Reading the RID in the Intel
depending on the state of a register select flip-flop. Following reset, the register select
flip flop is reset and the SRID is returned when the RID is read at offset 08h. The SRID
value reflects the actual product stepping. To select the CRID value, BIOS/configuration
software writes a key value of 79h to Bus 0, Device 0, Function 0 (ESI port) of the
Intel
select flip-flop and causes the CRID to be returned when the RID is read at offset 08h.
The RID register in the ESI port (Bus 0 device 0 Function 0) is a “write-once” sticky
register and gets locked after the first write. This causes the CRID to be returned on all
subsequent RID register reads. Software should read and save all device SRID values
by reading Intel
register select flip flop.
The RID values for all devices and functions in the Intel
controlled by the SRID/CRID register select flip flop, thus writing the key value (79h) to
the RID register in Bus 0, Device 0, Function 0 sets all Intel
registers to return the CRID. Writing to the RID register of other devices has no effect
on the SRID/CRID register select flip-flop. Only a power good reset can change the RID
selection back to SRID.
1. Even though the contents of the RID have an attribute as “RO”, it is ultimately dictated by the comparator flop
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
2. Compatible Revision ID (CRID): The CRID functionality gives BIOS the flexibility
7:4
3:0
Bit
(attribute “RWOST” in Device 0, function 0) that selects between the CRID/SRID outputs. The comparator is
set by BIOS/SW writing a specific value to offset 08h in dev0, fn 0 based on
Controller Hub Chipset Implementation of SRID and CRID Registers.”
to load OS drivers optimized for a previous revision of the silicon instead of the
current revision of the silicon in order to reduce drivers updates and minimize
changes to the OS image for minor optimizations to the silicon for yield
improvement, or feature enhancement reasons that do not negatively impact the
OS driver functionality.
®
5100 MCH Chipset’s RID register at offset 08h. This sets the SRID/CRID register
Attr
RO
RO
0, 2-7, 8
0
08h
16
0, 1, 2
08h
21, 22
0
08h
®
Default
5100 MCH Chipset RID registers before setting the SRID/CRID
0h
0h
Major Revision
Steppings which require all masks to be regenerated
1000: A stepping for the Intel
1001: B stepping for the Intel
1010: C stepping for the Intel
Others: Reserved
This field is set appropriately by the hardware based on the current stepping
and may differ from this default value.
Minor Revision
Incremented for each stepping which does not modify all masks. Reset for
each major revision
0h: M0 stepping
1h: M1 stepping
2h: M2 stepping
Others: Reserved
Note:
®
5100 MCH Chipset returns either the SRID or CRID
The Metal steppings indicated are a subset of the Major revision. For
example, an A stepping with M0 as minor revision typically means A0.
The field will be set appropriately
1
.
Intel
®
®
®
®
5100 MCH Chipset
5100 MCH Chipset as an example
5100 MCH Chipset as an example
Description
5100 MCH Chipset—Register Description
®
5100 MCH Chipset are
®
5100 MCH Chipset RID
Figure 11, “Intel® 5100 Memory
Order Number: 318378-005US
1
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July 2009