ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 108

• Manufacturer Part Number: ISP1760ET,557
• Manufacturer: NXP Semiconductors

Specifications of ISP1760ET,557

• Package Type: TFBGA
• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 57. Interrupt Enable register (address 0314h) bit
Table 58. Interrupt Enable register (address 0314h)
Table 59. ISO IRQ Mask OR register (address 0318h)
Table 60. INT IRQ Mask OR register (address 031Ch)
Table 61. ATL IRQ Mask OR register (address 0320h)
Table 62. ISO IRQ Mask AND register (address 0324h)
Table 63. INT IRQ Mask AND register (address 0328h)
Table 64. ATL IRQ Mask AND register (address 032Ch)
Table 65. High-speed bulk IN and OUT:
Table 66. High-speed bulk IN and OUT:
Table 67. High-speed isochronous IN and OUT:
Table 68. High-speed isochronous IN and OUT:
Table 69. High-speed interrupt IN and OUT:
Table 70. High-speed interrupt IN and OUT:
Table 71. Microframe description . . . . . . . . . . . . . . . . . .70
Table 72. Start and complete split for bulk:
Table 73. Start and complete split for bulk:
Table 74. SE description . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 75. Start and complete split for isochronous:
Table 76. Start and complete split for isochronous:
Table 77. Start and complete split for interrupt:
Table 78. Start and complete split for interrupt:
Table 79. Microframe description . . . . . . . . . . . . . . . . . .82
Table 80. SE description . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 81. Power consumption . . . . . . . . . . . . . . . . . . . . .84
Table 82. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 83. Recommended operating conditions . . . . . . . .85
Table 84. Static characteristics: digital pins . . . . . . . . . . .86
Table 85. Static characteristics:
Table 86. Static characteristics: USB interface block
Table 87. Static characteristics: REF5V . . . . . . . . . . . . .87
Table 88. Dynamic characteristics: system clock
Table 89. Dynamic characteristics: CPU interface
Table 90. Dynamic characteristics: high-speed
ISP1760_4
Product data sheet
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .55
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
bit description . . . . . . . . . . . . . . . . . . . . . . . . .56
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .59
bit description . . . . . . . . . . . . . . . . . . . . . . . . .60
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .63
bit description . . . . . . . . . . . . . . . . . . . . . . . . .64
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .67
bit description . . . . . . . . . . . . . . . . . . . . . . . . .68
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .71
bit description . . . . . . . . . . . . . . . . . . . . . . . . .72
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .75
bit description . . . . . . . . . . . . . . . . . . . . . . . . .76
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .79
bit description . . . . . . . . . . . . . . . . . . . . . . . . .80
PSW1_N, PSW2_N, PSW3_N . . . . . . . . . . . .86
(pins DM1 to DM3 and DP1 to DP3) . . . . . . . .86
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Rev. 04 — 4 February 2008
Table 91. Dynamic characteristics: full-speed source
Table 92. Dynamic characteristics: low-speed
Table 93. Register or memory write . . . . . . . . . . . . . . . . 90
Table 94. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 95. Register access . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 96. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 97. DMA read (single cycle) . . . . . . . . . . . . . . . . . 93
Table 98. DMA write (single cycle) . . . . . . . . . . . . . . . . . 94
Table 99. DMA read (multi-cycle burst) . . . . . . . . . . . . . . 95
Table 100.DMA write (multi-cycle burst) . . . . . . . . . . . . . 96
Table 101.SnPb eutectic process (from J-STD-020C) . . 100
Table 102.Lead-free process (from J-STD-020C) . . . . . 100
Table 103.Suitability of through-hole mount
Table 104.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 105.Revision history . . . . . . . . . . . . . . . . . . . . . . . 104
source electrical characteristics . . . . . . . . . . . 88
electrical characteristics . . . . . . . . . . . . . . . . . 89
source electrical characteristics . . . . . . . . . . . 89
IC packages for dipping and wave soldering . 102
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
ISP1760
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