ISP1760ET,557 NXP Semiconductors, ISP1760ET,557 Datasheet - Page 19



Manufacturer Part Number
NXP Semiconductors

Specifications of ISP1760ET,557

Package Type
Pin Count
Lead Free Status / RoHS Status
NXP Semiconductors
Product data sheet
7.3.1 PIO mode access, memory read cycle
7.3 Accessing the ISP1760 host controller memory: PIO and DMA
Both the CPU interface logic and the USB host controller require access to the internal
ISP1760 RAM at the same time. The internal arbiter controls these accesses to the
internal memory, organized internally on a 64-bit data bus width, allowing a maximum
bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the
CPU interface and the internal USB host controller.
The CPU interface of the ISP1760 can be configured for a 16-bit or 32-bit data bus width.
When the ISP1760 is configured for a 16-bit data bus width, the upper unused 16 data
lines must be pulled up to V
together to a single 10 k pull-up resistor. The 16-bit or 32-bit data bus width
configuration is done by programming bit 8 of the HW Mode Control register. This will
determine the register and memory access types in both PIO and DMA modes. All
accesses must be word-aligned for 16-bit mode and double word aligned for 32-bit mode,
where one word = 16 bits. When accessing the host controller registers in 16-bit mode,
the register access must always be completed using two subsequent accesses. In the
case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the
number of bursts that will complete a certain transfer length.
In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA
mode, the data validation is performed by DACK, instead of CS_N, together with the
WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the
ISP1760 DMA is enabled.
The following method has been implemented to reduce the read access timing in the case
of a memory read:
The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an
appropriate value is written to this register.
Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to pre-fetch data for the memory read of that bank.
For every subsequent read operation executed at a contiguous address, the address
pointer corresponding to that bank is automatically incremented to pre-fetch the next
data to be sent to the CPU.
Memory read accesses for multiple banks can be interleaved. The FIFO block
handles the multiplexing of appropriate data to the CPU.
The address written to the Memory register is incremented and used to successively
pre-fetch data from the memory irrespective of the value on the address bus for each
bank, until a new value for a bank is written to the Memory register. This is valid only
when the address refers to the memory space (400h to FFFFh).
For example, consider the following sequence of operations:
– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.
When RD_N is asserted for three cycles with A[17:16] = 01, the returned data
corresponds to addresses 4000h, 4004h and 4008h.
Rev. 04 — 4 February 2008
. This can be achieved by connecting DATA[31:16] lines
Embedded Hi-Speed USB host controller
© NXP B.V. 2008. All rights reserved.
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