ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 114

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ALXD800EEXJ2VD C3

Manufacturer Part Number
ALXD800EEXJ2VD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VD C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
5.5.2.7
MSR Address
Type
Reset Value
5.5.2.8
MSR Address
Type
Reset Value
114
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:23
21:16
63:16
15:8
15:8
Bit
7:0
Bit
7:0
22
Performance Event Counter 0 Select MSR (PERF_SEL0_MSR
Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)
Name
RSVD
PC_EN
RSVD
PC0_UMASK
PC0_EVENT
Name
RSVD
PC1_UMASK
PC1_EVENT
RSVD
00000186h
R/W
00000000_00000000h
00000187h
R/W
00000000_00000000h
33234H
RSVD
Description
Reserved. Write as read.
Performance Event Counters 0 and 1 Enable.
0: Disable counters.
1: Enable counters.
Reserved. Write as read.
Performance Event Counter 0 Unit Mask. Selects sub-events.
00h: All sub-events counted.
Performance Event Counter 0 Event Select Value. See individual module chapters for
performance event selections.
Description
Reserved. Write as read.
Performance Event Counter 1 Unit Mask. Selects sub-events.
00h: All sub-events counted.
Performance Event Counter 1 Event Select Value. See individual module chapters for
performance event selections.
PERF_SEL0_MSR Bit Descriptions
PERF_SEL1_MSR Bit Descriptions
PERF_SEL0_MSR Register Map
PERF_SEL1_MSR Register Map
RSVD
RSVD
RSVD
PC0_UMASK
PC1_UMASK
AMD Geode™ LX Processors Data Book
9
9
8
8
CPU Core Register Descriptions
7
7
6
6
5
5
PC0_EVENT
PC1_EVENT
4
4
3
3
2
2
1
1
0
0

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