ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 353

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.15
6.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING)
DC Memory Offset 0E4h
Type
Reset Value
This register contains vertical active and total timing information. These parameters pertain ONLY to even fields in inter-
laced display modes (The DC_V_ACTIVE_TIMING register (DC Memory Offset 050h) will take effect for odd fields in inter-
laced display modes.) Settings written to this register will not take effect until the start of the frame or interlaced field after
the timing register update bit is set (DC Memory Offset 008h[6] = 1).
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:27
26:16
15:11
10:0
Bit
RSVD
Even Field Vertical Timing Registers
Name
RSVD
V_TOTAL
RSVD
V_ACTIVE
R/W
xxxxxxxxh
Description
Reserved. These bits should be programmed to zero.
Vertical Total. This field represents the total number of lines for a given frame scan
minus 1. Note that the value is necessarily greater than the V_ACTIVE field (bits 10:0])
because it includes border lines and blanked lines.
Reserved. These bits should be programmed to zero.
Vertical Active. This field represents the total number of lines for the displayed portion of
a frame scan minus 1. Note that for flat panels, if this value is less than the panel active
vertical resolution (V_PANEL), the parameters V_BLANK_START, V_BLANK_END,
V_SYNC_START, and V_SYNC_END should be reduced by the following value
(V_ADJUST) to achieve vertical centering:
If graphics scaling is enabled (and interleaved display is enabled), this value represents
the height of the final (scaled) field to be displayed. The height of the frame buffer image
may be different in this case; FB_ACTIVE (DC Memory Offset 5Ch) is used to program
the horizontal and vertical active values in the frame buffer when graphics scaling is
enabled.
DC_V_ACTIVE_EVEN_TIMING Bit Descriptions
DC_V_ACTIVE_EVEN_TIMING Register Map
V_TOTAL
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
RSVD
9
8
33234H
7
V_ACTIVE
6
5
4
3
2
1
353
0