ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 513

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Security Block Register Descriptions
6.12
This section provides information on the registers associ-
ated with the Security Block (SB), including the Standard
GeodeLink Device (GLD) MSRs, the Security Block Spe-
cific MSRs (accessed via the RDMSR and WRMSR
instructions), and the Security Block Configuration/Control reg-
isters. Table 6-78 through Table 6-80 are register summary
AMD Geode™ LX Processors Data Book
MSR Address
MSR Address
SB Memory
58002000h
58002001h
58002002h
58002003h
58002004h
58002005h
58002006h
Offset
03Ch
000h
004h
008h
010h
014h
018h
020h
024h
028h
030h
034h
038h
040h
044h
Security Block Register Descriptions
Table 6-80. Security Block Configuration/Control Registers Summary
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
WO
WO
WO
WO
Table 6-78. Standard GeodeLink™ Device MSRs Summary
Register Name
SB Control A (SB_CTL_A)
SB Control B (SB_CTL_B)
SB AES Interrupt (SB_AES_INT)
SB Source A (SB_SOURCE_A)
SB Destination A (SB_DEST_A)
SB Length A (SB_LENGTH_A)
SB Source B (SB_SOURCE_B)
SB Destination B (SB_DEST_B)
SB Length B (SB_LENGTH_B)
SB Writable Key 0 (SB_WKEY_0)
SB Writable Key 1 (SB_WKEY_1)
SB Writable Key 2 (SB_WKEY_2)
SB Writable Key 3 (SB_WKEY_3)
SB CBC Initialization Vector 0
(SB_CBC_IV_0)
SB CBC Initialization Vector 1
(SB_CBC_IV_1)
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)
Register Name
GLD Control MSR (GLD_MSR_CTRL)
Table 6-79. Security Block Specific MSRs
tables that include reset values and page references where
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
00000000_00000000h
00000000_00000007h
00000000_00000019h
00000000_00000015h
00000000_00000000h
00000000_00000003h
00000000_001304xxh
Reset Value
Reset Value
Reset Value
00000000h
00000000h
00000007h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
33234H
Reference
Reference
Reference
Page 520
Page 521
Page 522
Page 522
Page 523
Page 523
Page 524
Page 524
Page 525
Page 525
Page 526
Page 526
Page 527
Page 527
Page 528
Page 515
Page 515
Page 516
Page 516
Page 518
Page 518
Page 519
513