ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 433

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Video Processor Register Descriptions
6.8.3.16 CRC Signature (CRC)
VP Memory Offset 088h
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:3
Bit
2
1
0
Name
RSVD (RO)
SIGVAL (RO)
SIGFR
SIGEN
R/W
00000000_00000000h
Description
Reserved (Read Only). Reads back as 0.
Signature Valid (Read Only). If this bit is set, the signature operation has completed
and the signature may be safely read from the 32-Bit CRC Signature Register (VP Mem-
ory Offset 090h).
Signature Free Run.
0: Disable. (Default). If this bit was previously set to 1, the signature process will stop at
1: Enable. If SIGNEN (bit 0) is set to 1, the signature register captures data continuously
Signature Enable.
0: Disable. The SIGVAL (bits [31:8]) is reset to 000001h in 24-bit mode or 000000h in 32-
1: Enable. When this bit is set to 1, the next falling edge of VSYNC is counted as the start
After a signature capture is complete, the SIGVAL (bit 2) can be read to determine the
CRC check status. In 32-bit CRC mode, the full 32-bit signature can be read from the 32-
Bit CRC Signature (VP Memory Offset 090h[31:0]). Then proceed to reset SIGEN, which
initializes SIGVAL as an essential preparation for the next round of CRC checks.
If SIGFR (bit 1) is set to 1, the signature register captures the pixel data signature con-
If SIGFR (bit 1) is cleared to 0, a signature is captured one frame at a time, starting
the end of the current frame (i.e., at the next falling edge of VSYNC).
across multiple frames.
bit mode and held (no capture). (Default)
of the frame to be used for CRC checking with each pixel clock beginning with the next
VSYNC.
tinuously across multiple frames.
from the next falling VSYNC.
CRC Bit Descriptions
CRC Register Map
RSVD
RSVD
9
8
33234H
7
6
5
4
3
2
1
433
0