ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 268

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.4.2.13 BLT Mode (GP_BLT_MODE)
GP Memory Offset 40h
Type
Reset Value
Writing to this register configures the BLT mode and initiates the rendering of the BLT. If a BLT or vector operation is already
in progress when this register is written, the BLT pending bit in GP_BLT_STATUS (GP Memory Offset 44h) is set and the
BLT is queued to begin when the current operation is complete. Software should not write to any register (other than
GP_HOST_SRC if required) while the BLT pending bit is set since it will corrupt the pending BLT. Setting the TH bit causes
the BLT operation to wait until the next VBLANK before beginning. Software may still queue another operation behind a
throttled BLT as long as the BLT pending bit is clear.
268
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:12
7:6
5:3
1:0
Bit
11
10
9
8
2
Name
RSVD
CP
TH
X
Y
SM
RSVD
DR
SR
WO
00000000h
33234H
Description
Reserved. Write to 0.
Checkpoint. Generates interrupt when this BLT is completed if checkpoint interrupt is
enabled.
Throttle. BLT does not begin until next VBLANK.
0: Disable.
1: Enable.
X Direction.
0: Indicates a positive increment for the X position.
1: Indicates a negative increment for the X position.
Y Direction.
0: Indicates a positive increment for the Y position.
1: Indicates a negative increment for the Y position.
Source Mode. Specifies the format of the source data.
00: Source is color bitmap.
01: Source is unpacked monochrome.
10: Source is byte-packed monochrome.
11: Undefined.
Reserved. Write as read.
Destination Required.
0: No destination data is required.
1: Indicates that destination data is needed from frame buffer.
Source Required.
00: No source data.
01: Source from frame buffer.
10: Source from GP_HST_SRC register (GP Memory Offset 48h).
11: Undefined.
RSVD
GP_BLT_MODE Bit Descriptions
GP_BLT_MODE Register Map
TH
Graphics Processor Register Definitions
AMD Geode™ LX Processors Data Book
X
9
Y
8
7
SM
6
5
RSVD
4
3
DR
2
1
SR
0