ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 99

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5
All CPU Core registers are Model Specific Registers
(MSRs) and are accessed via the RDMSR and WRMSR
instructions.
Each module inside the processor is assigned a 256 regis-
ter section of the address space. The module responds to
any reads or writes in that range. Unused addresses within
a module’s address space are reserved, meaning the mod-
ule returns zeroes on a read and ignores writes. Addresses
that are outside all the module address spaces are invalid,
AMD Geode™ LX Processors Data Book
000000C1h
000000C2h
00002000h
00002001h
00002002h
00002003h
00002004h
00002005h
00000010h
00000174h
00000175h
00000176h
00000186h
00000187h
00001100h
00001102h
00001108h
00001109h
Address
Address
MSR
MSR
CPU Core Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
W
Table 5-12. Standard GeodeLink™ Device MSRs Summary
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI) - Not Used
GLD Error MSR (GLD_MSR_ERROR) - Not Used
GLD Power Management MSR (GLD_MSR_PM) -
Not Used
GLD Diagnostic Bus Control MSR
(GLD_MSR_DIAG)
Register Name
Time Stamp Counter MSR (TSC_MSR)
Performance Event Counter 0 MSR
(PERF_CNT0_MSR)
Performance Event Counter 1 MSR
(PERF_CNT1_MSR)
SYSENTER/SYSEXIT Code Segment Selector
MSR (SYS_CS_MSR)
SYSENTER/SYSEXIT Stack Pointer MSR
(SYS_SP_MSR)
SYSENTER/SYSEXIT Instruction Pointer MSR
(SYS_IP_MSR)
Performance Event Counter 0 Select MSR
(PERF_SEL0_MSR
Performance Event Counter 1 Select MSR
(PERF_SEL1_MSR)
Instruction Fetch Configuration MSR
(IF_CONFIG_MSR)
IF Invalidate MSR (IF_INVALIDATE_MSR)
IF Test Address MSR (IF_TEST_ADDR_MSR)
IF Test Data MSR (IF_TEST_DATA_MSR)
Table 5-13. CPU Core Specific MSRs Summary
meaning a RDMSR/WRMSR instruction attempting to use
the address generates a General Protection Fault.
The registers associated with the CPU Core are the Stan-
dard GeodeLink™ Device MSRs and CPU Core Specific
MSRs. Table 5-12 and Table 5-13 are register summary
tables that include reset values and page references where
the bit descriptions are provided. Note that the standard
GLD MSRs for the CPU Core start at 00002000h.
00000000_C09B0000h
00000000_00000000h
00000000_000864xxh
00000000_00000320h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00005051h
00000000_00000000h
00000000_xxxxxxxxh
Reset Value
Reset Value
33234H
Reference
Reference
Page 108
Page 108
Page 109
Page 109
Page 109
Page 109
Page 110
Page 110
Page 111
Page 112
Page 113
Page 113
Page 114
Page 114
Page 115
Page 118
Page 118
Page 119
99